1. Field of the Invention
The present invention is directed in general to the field of semiconductor devices. In one aspect, the present invention relates to high-performance complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) fabricated on hybrid substrates.
2. Description of the Related Art
To address the difference in electron and hole mobility values for NMOS and PMOS transistor devices formed on semiconductor wafers having a single crystal orientation, CMOS devices are increasingly fabricated with hybrid substrates with different surface orientations using semiconductor-on-insulator (SOI) wafer bonding to provide PMOS and NMOS devices with their own optimized crystal orientation. Prior attempts to integrate dual or hybrid substrates have used epitaxial growth to form one of the crystal surface orientations, but have resulted in non-uniform silicon step/recess heights between the different crystal surfaces after the grown epitaxial material is polished with a chemical mechanical polish (CMP) step. The different surface heights are caused by pattern density effects and the CMP dishing sensitivity of structures of varying sizes and structure density which create variations in post-CMP uniformity. Another source of surface height difference is the presence of a polish stop layer used during the shallow trench isolation (STI) and CMP processing steps. An example is depicted in FIGS. 1-3 which show a device 10 having two crystal surface orientations—surface 1 having a first orientation and a semiconductor-on-insulator (SOI) layer 3 having a second orientation—separated by buried oxide layers 2 and isolation regions 4 and covered by nitride layers 6. As shown in FIG. 1, an epi silicon layer 7 (having the first orientation) is formed in an opening in the device 10. After the epi silicon 8 is polished (as depicted in FIG. 2), the surface of the epi silicon 8 is recessed below the nitride layer 6. However, when the nitride layer 6 is stripped (as depicted in FIG. 3), the epi silicon 8 is higher than the underlying SOI layer 3. The non-uniform surface heights impair photolithography control and increase dispersion of device parametrics and performance, especially when the sizes and density of the device structures vary.
Accordingly, a need exists for a semiconductor manufacturing process which improves the post-CMP planarity of the dual surface orientation devices. There is also a need for a fabrication process which avoids the process and performance limitations associated with non-uniform surface heights and minimizes surface step heights in a Dual-Surface Orientation (DSO) integration. In addition, there is a need for improved semiconductor processes and devices to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.